(1) Field of the Invention
The invention relates to DMA (Direct Memory Access) control structures, more particularly, to the methods and apparatus for controlling a DMA processor through a linear list of DMA descriptors in memory.
(2) Prior Art
Advanced DMA controllers typically use a linked list in memory to chain together a sequence of DMA transfer descriptors. Although this makes efficient use of memory, this method requires a complex DMA controller capable of traversing a list. This method, therefore, can be a burden on the central processing unit (CPU) to update the list.
One simple method by which a DMA controller operates is where the microprocessor writes directly into the DMA controller using an input/output (I/O) access with a special command in the microprocessor's language. This method of controlling the DMA controller during an I/O transfer is fairly slow and requires the microprocessor to monitor and direct the DMA controller. Thus, the DMA controller sits in an idle state while the microprocessor is getting ready to give the DMA controller the next command.
FIG. 1 is a flow diagram illustrating the general steps followed by an exemplary prior art method. In this prior art method, a CPU takes direct control of the DMA. In step 100, the CPU reads a status register to determine if a DMA transfer Is complete. The CPU continues to read the status register until the DMA transfer is complete, then in step 102, the DMA controller is checked to see if it is an idle state. In step 104, the CPU writes a control word to the DMA's mode register which describes the set-up of the DMA controller such as the width of the data being transferred. In step 106, the CPU writes the source address from which the data is being transferred from to a source address register, and in step 108 the CPU writes the destination address to which the data is being transferred to a destination address register.
In step 110, the CPU writes to a length register and in step 112, the CPU writes a start command to the DMA controller. In step 114, the DMA controller begins performing a DMA transfer. In step 116, when the DMA controller completes its DMA transfer, the DMA controller clears the status register to indicate to the CPU that the DMA transfer is complete. In this prior art method, the CPU must continuously monitor the DMA start and end activities by polling the status register and must execute various commands to write registers creating an inefficient use of CPU time.
FIG. 2 illustrates a prior art method using a more advanced DMA controller. Linked descriptors in memory 200 are pointed to by first descriptor pointer/internal register 202. The DMA controller reads commands from the CPU which the CPU has deposited into the memory for the DMA controller to fetch. The deposited descriptors are entered in the linked list in the memory.
With advanced DMA controllers, the microprocessor creates a table of commands, typically a linked list. The microprocessor may write a starting address to the DMA controller which points into the memory where the microprocessor has chosen to insert a starting address, a length, a destination address and a source address. Thus, the commands are linked together, for example with a link to a memory space containing a zero to indicate the end of the list. A drawback to this method is that in order for the microprocessor to update this linked list, it must spend time calculating the offset to the next block of instructions. The microprocessor must then insert the new pointer to the next block of instructions.
There is a great need for a more efficient method of updating DMA controller entries in memory, which dispenses with the need for the CPU to continuously monitor and poll the DMA activities. In addition to saving CPU time, such a method should save the DMA controller time by allowing for a more efficient method of reading new descriptor entries.